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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
32 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.12 Power-saving modes
The device provides two power saving modes of operation for applications where power
consumption is critical. The two modes are idle and Power-down, see Table 31.
6.12.1 Idle mode
Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program
counter is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during
this mode.
2
EX1
External Interrupt 1 Enable.
1
ET0
Timer 0 Overow Interrupt Enable.
0
EX0
External Interrupt 0 Enable.
Table 27.
IP - Interrupt priority low register (address B8H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
PT2
PS
PT1
PX1
PT0
PX0
Table 28.
IP - Interrupt priority low register (address B8H) bit description
Bit
Symbol
Description
7:6
-
Reserved
5
PT2
Timer 2 Interrupt Priority Low Bit.
4
PS
Serial Port Interrupt Priority Low Bit.
3
PT1
Timer 1 Interrupt Priority Low Bit.
2
PX1
External Interrupt 1 Priority Low Bit.
1
PT0
Timer 0 Interrupt Priority Low Bit.
0
PX0
External Interrupt 0 Priority Low Bit.
Table 29.
IPH - Interrupt priority high register (address B7H) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Table 30.
IPH - Interrupt priority high register (address B7H) bit description
Bit
Symbol
Description
7:6
-
Reserved
5
PT2H
Timer 2 Interrupt Priority High Bit.
4
PSH
Serial Port Interrupt Priority High Bit.
3
PT1H
Timer 1 Interrupt Priority High Bit.
2
PX1H
External Interrupt 1 Priority High Bit.
1
PT0H
Timer 0 Interrupt Priority High Bit.
0
PX0H
External Interrupt 0 Priority High Bit.
Table 26.
IE - Interrupt enable register (address A8H) bit description …continued
Bit
Symbol
Description
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